Data output buffer of a synchronous semiconductor memory device

ABSTRACT

A data output buffer is used for a synchronous semiconductor memory device carrying out a data read/write operation in synchronism with an externally supplied clock. The semiconductor memory device includes a first shift register having a plurality of clock stages for transmitting a RAS signal in response to the clock; a circuit for extracting a data output margin signal from a predetermined stage among the stages of the first shift circuit; first latch circuits each receiving the data output margin signal, for generating a plurality of first latency signals having information on the RAS signal by combining row address signals and the signals extracted from the respective clock stages of the first shift circuit; a second shift circuit having a plurality of clock stages for transmitting a CAS signal in response to the clock; second latch circuits each receiving the data output margin signal, for generating a plurality of second latency signals having information on the CAS signal by combining column address signals and the signals extracted from the respective clock stages of the second shift circuit; and a latency combination circuit receiving the first and second latency signals, for generating a data output control signal to the data output buffer, so that the data output buffer can generate data output even during a RAS precharge cycle.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor memory device, and moreparticularly to a data output buffer used for a synchronoussemiconductor memory device performing a data read/write operations insynchronism with an externally supplied clock.

2. Description of the Related Art

A dynamic RAM, a typical readable/writable memory, is essentiallyprovided with a row address strobe (hereinafter referred to as "RAS")signal and a column address strobe (hereinafter referred to as "CAS")signal, respectively supplied from an external circuit such as a CPU, soas to read or write data from/into a memory cell therein.

FIG. 1A shows timing diagram for a read cycle in a conventional dynamicRAM. A row address signal RA is input to the memory device after a RASsignal has been enabled to "low" logic state followed by a columnaddress signal CA being input in response to a CAS signal being enabledto "low" logic state while the RAS signal is held active. During thistime, data stored in a memory cell corresponding to an address signalinput is sensed by a sense amplifier. The data sensed is output througha data output buffer. When this takes place, data paths of the dataoutput buffer are connected or disconnected according to an outputenable signal OE (see FIG. 1B). It is well known that an output enablesignal OE is generated by using a control clock supplied from a CPU andfrom a signal generated in the memory chip for data sensing.

In a conventional dynamic RAM, during one CAS cycle, only one bit of theoutput data is output in page mode while four bits of output data areoutput in nibble mode. Data output operations are inhibited once the RASsignal is disabled at which time the memory device enters a prechargemode. In practice, however, during every read cycle, a time interval(t_(RAC)) spanning from an enabling point of the RAS signal to a pointin time when the output data is substantially generated responding tothe RAS signal, is essentially required. A data input/output line isequalized and precharged during the time interval from when data isoutput from the memory chip during an RAS cycle to when a next data isagain output at the next RAS cycle. Thus, it should be apparent that theabove mentioned time interval t_(RAC) is much longer than a timerequired for equalizing and precharging the data input/output line. Thatis, a time loss is unnecessarily caused between a current data outputcycle and a next data output cycle.

A conventional dynamic RAM also performs data access operationsasynchronously. A data bus and an input/output bus are equalized andprecharged at various time intervals between a current and a next readcycle, between a read and a write cycle, and between a current and anext write cycle. Moreover, a memory device formed on an integratedcircuit receives TTL level signals provided from a CPU and converts themto CMOS level signals before using them. As is well known, present dayCPU operation speeds are far more improved than the speeds ofconventional memory devices. Manufacturers have as a result recognizedthe need to make the operation speeds of memory devices faster, whichwould result in shorter data access times.

However, the operation speed of a conventional asynchronous dynamic RAMcan only be increased so much and no more given its unique operationstructure. To solve the problem of slow data access times, a memorydevice is needed that is capable of carrying out a data read/writeoperation in synchronism with an external clock supplied from a CPU.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a dataoutput buffer capable of carrying out an effective data outputoperation, used for a memory device operating in synchronism with aclock supplied from an external source.

It is another object of the present invention to provide a semiconductormemory device having a data output buffer controlling device capable ofoutputting data even during a RAS precharge cycle.

It is also another object of the present invention to provide asemiconductor memory device having a device for controlling a dataoutput buffer in synchronism with a clock supplied from an externalsource.

According to an aspect of the present invention, a semiconductor memorydevice includes a first shift register having a plurality of clockstages for transmitting a RAS signal in response to the clock; a circuitfor extracting a data output margin signal from a predetermined stageamong the stages of the first shift circuit; first latch circuits eachreceiving the data output margin signal, for generating a plurality offirst latency signals having information on the RAS signal by combiningrow address signals and the signals extracted from the respective clockstages of the first shift circuit; a second shift circuit having aplurality of clock stages for transmitting a CAS signal in response tothe clock; second latch circuits each receiving the data output marginsignal, for generating a plurality of second latency signals havinginformation on the CAS signal by combining column address signals andthe signals extracted from the respective clock stages of the secondshift circuit; and a latency combination circuit receiving the first andsecond latency signals, for generating a data output control signal tothe data output buffer, so that the data output buffer can generate dataoutput even during a RAS precharge cycle.

The present invention will now be described more specifically withreference to the drawings attached only by way of example.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a timing diagram used to describe a data outputting processof a conventional dynamic RAM;

FIG. 1B is a circuit diagram of a data output buffer of a conventionaldynamic RAM;

FIG. 2 shows a pin configuration of a dynamic RAM using an externalsystem clock, to which the present invention is applied;

FIG. 3 is a schematic diagram of a data output buffer and a controlcircuit therefor according to an embodiment of the present invention;

FIG. 4A is a detailed circuit diagram of the RAS signal processor 100shown in FIG. 3;

FIG. 4B is a detailed circuit diagram of the CAS signal processor 200shown in FIG. 3;

FIG. 4C is a timing diagram of a read operation in the device of FIG. 3;

FIG. 4D is a timing diagram of yet another read operation in the deviceof FIG. 3;

FIG. 5 is a schematic diagram of a data output buffer and a controlcircuit therefor according to another embodiment of the presentinvention;

FIG. 6A is a detailed circuit diagram of the RAS signal processor 100'shown in FIG. 5;

FIG. 6B is a detailed circuit diagram of the CAS signal processor 200'shown in FIG. 5;

FIG. 6C is a timing diagram of a read operation in the device of FIG. 5;and

FIG. 6D is a timing diagram of yet another read operation in the deviceof FIG. 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A data output buffer according to the present invention is applied to amemory device 10 that processes all signals in response to a clock(hereinafter referred to as "system clock") supplied from an externalsource, as shown in FIG. 2 which illustrates a basic pin configurationof a synchronous dynamic RAM operating in synchronism with the systemclock SC. In this figure, Vcc indicates a power supply pin, W a writecontrol signal input pin, D_(IN) a data input pin, A0-A10 address inputpins, D_(OUT) a data output pin, TF a test pin, Vss a ground voltagepin, RAS a row address strobe signal input pin, and CAS a column addressstrobe signal input pin. Moreover, a pin SC for receiving a system clockfrom a CPU (not shown) is illustrated.

The various embodiments of the present invention will be discussed withreference to a dynamic RAM environment, for the sake of simplicity. Itis noted, however, that other memory devices, such as a static RAM, canbe used to implement the inventive concept of the presently disclosedembodiments. In the following description of the preferred embodimentsof the present invention, data stored in a memory cell is accessed insynchronism with the system clock as a reference clock which operates asa reference clock.

FIG. 3 shows a generation of a latency signal RCLAT for controlling adata output buffer 400 and how the data output buffer 400 operates usingthe latency signal RCLAT. As shown in FIG. 3, a RAS signal processor 100receives a system clock SC, a RAS master clock PIR, and row addresscombination signals RL1-RLm and outputs RAS latency signals RLINF1 toRLINFi, and a data output margin signal PIRD used to ensure theoutputting of data even during a RAS precharge cycle. RAS master clockPIR is a signal generated in synchronism with system clock SC which istriggered up after the RAS signal has entered into its active cycle oris enabled. In ints present context, the term "RAS latency" refers to atime interval from an enabling point of the RAS signal to a point intime when an output is generated responding to the RAS signal.

CAS signal processor 200 is also provided which receives the systemclock SC, a CAS master clock PIC, the column address combination signalsCL1-CLn, and the data output margin signal PIRD generated from the RASsignal processor 100, and generates CAS latency signals CLINF1 toCLINFj. The CAS master clock PIC, as with signal PIR, is a signalgenerated in synchronism with system clock SC which is triggered upafter a CAS signal has entered its active cycle or is enabled. The term"CAS latency" refers to a time interval from an enabling point of theCAS signal to a point in time when an output is generated responding tothe CAS signal.

The RAS latency signals RLINF1-RNLINFi and CAS latency signalsCLINF1-CLINFj, respectively generated from the RAS signal processor 100and the CAS signal processor 200 are input into a latency combinationcircuit 300 comprised of logic gates such as NOR gates, a NAND gate, andinverters. The latency combination circuit 300, by using the RAS latencysignals RLINF1-RLINFi and the CAS latency signals CLINF1-CLINFj,generates the latency signal RCLAT into which the information of the RASlatency signals and the CAS latency signals is included and then, inputsthe latency signal RCLAT to the data output buffer 400.

The latency signal RCLAT controls data transmission paths of the dataoutput buffer 400 and a time interval thereof during which the data isoutput. Latency signal RCLAT serves as the output enable signal OE inthe conventional data output buffer shown in FIG. 1B. It should be notedthat latency signal RCLAT can be generated from both the RAS signal andthe CAS signal, or from either of those signals.

When using only an RAS signal according to one embodiment of the presentinvention shown in FIG. 3, for example, the latency signal RCLAT can begenerated by changing one of RAS latency signals RLINF1-RLINFj to anactive state using the RAS signal processor 100 only and removing theCAS signal processor 200, and then inputting the activated signal intolatency combination circuit 300.

FIGS. 4A and 4B are examples of the detailed circuit configurations ofthe RAS signal processor 100 and the CAS signal processor 200 that areblock-marked respectively in FIG. 3. As shown in FIG. 4A, the RAS signalprocessor 100 is comprised of a shift register 110 having m clock stagesRCS1-RCSm, m-1 NAND gates RND2-RNDm each receiving the row addresssignals RL2-RLm and the voltage at nodes RN2-RNm respectively located inall the clock stages except the first clock stage, inverters I13, I14connected in series for supplying the data output margin signal PIRDthat had been extracted from a node of a clock stage (in the case ofFIG. 4A, a node RN3 in the third clock stage RCS3) to the CAS signalprocessor 200, NAND gates 106 . . . 108 each receiving signals outputfrom corresponding two adjacent NAND gates among the NAND gatesRND2-RNDm, NAND gates 107 . . . 109 each receiving the data outputmargin signal PIRD. Latch circuits RNDL1-RNDLi are thus providedgenerating i RAS latency signals RLINF1-RLINFi.

Of latch circuits RNDL1-RNDLi, the respective latch circuits connectedto the clock stages positioned before (or left hand side of) a clockstage from which the data output margin signal PIRD is extracted, arecoupled to the output signals of the NAND gates receiving the signalsoutput from the adjacent two clock stages among the clock stagesRCS2-RCSm, and the rest of the latch circuits positioned after (or righthand side of) a clock stage from which the data output margin signalPIRD is extracted are coupled to the NAND gates receiving the signalsoutput from consecutive three clock stages. If the data output marginsignal PIRD is extracted from a node RN1 of the first clock stage RCS1instead of the node RN3 of the third clock stage RCS3, all the latchcircuits RNDL1-RNDLi would receive the outputs of the consecutive threeNAND gates RND1/RND2/RND3; RND4/RND5/RND6; . . . ; andRNDm-2/RNDm-1/RNDm, respectively.

First clock stage RCS1 is comprised of a transfer gate TG1 and a latchL1 connected in series and receives the RAS master clock PIR viainverters I11 and I12 connected in series. Of transfer gates TG1-TG10included in the respective stages, p-type transfer gates TG1, TG3, TG5,TG7, TG9 and n-type transfer gates TG2, TG4, TG6, TG8, TG10 arealternatively arranged and are all controlled according to the systemclock SC. Accordingly, when system clock SC goes to logic "high" state,n-type transfer gates TG2, TG4, TG6, TG8, TG10 are all turned on.According to the embodiment of FIG. 4A, 2 bits of output data arefurther generated even after the RAS signal has entered a prechargecycle because data output margin signal PIRD is extracted from the nodeRN3 of third clock stage RCS3. However, the extracting position of dataoutput margin signal PIRD can be changed according to how many bits ofthe output data should be generated even during the RAS precharge cycle.A relationship between an extracting position of data output marginsignal PIRD and the number of output data bits desired to be generatedduring an RAS precharge cycle will be explained in detail herebelow.

Referring to FIG. 4B, the CAS signal processor 200 has a shift register210 composed of n clock stages CCS1-CCSn as in the case of a circuitconfiguration of the RAS signal processor 100 illustrated in FIG. 4A, aswell as n NAND gates CND1-CNDn each receiving the signals at nodesCN1-CNn of the respective clock stages CCS1-CCSn and column addresscombination signals CL1-CLn. Of the NAND gates CND1-CNDn, the signalsbeing output from two adjacent clock stages are input to NAND gates 207. . . 209, respectively. NAND gates 208 . . . 210 each receiving theoutput of a NOR gate 206 for receiving the data output margin signalPIRD and a write master clock PIWR to notify the state of the dataoutput margin signal PIRD, together with the NAND gates 207 and 209,constitute j latch circuits CNDL1-CNDLj for generating j CAS latencysignals CLINF1-CLINFj.

FIG. 4C illustrates a timing operation for the case where data outputmargin signal PIRD is extracted from node RN3 as shown in FIG. 4A. FIG.4D shows a timing operation for the case where data output margin signalPIRD is extracted from node RN2 instead (not shown).

Referring to FIG. 4C, after the RAS signal has entered its active cyclelogic "low" state, RAS master clock PIR is enabled to logic "high" statein synchronism with a rising edge of system clock SC. Similalrly, afterthe CAS signal has entered its active cycle logic "low" state, CASmaster clock PIC is enabled to logic "high" state in synchronism with arising edge of system clock SC. As shown in FIG. 4A, the RAS masterclock PIR supplied to the clock stage RCS1 is transferred to node RN3 ata rising edge of the third pulse of the system clock signal SC. Itshould be noted that an initial value of each clock stage of shiftregisters 110 and 210 respectively illustrated in FIGS. 4A and 4B is thelogic "low" state and that only row address signal RL3 among the rowaddress combination signals RL2-RLm is in logic "high" state. Similarly,only signal CL2 among the column address combination signals CL1-CLn isin logic "high" state.

A detailed description the setting of row address combination signalshas been omitted as such is well known in the field. It is noted fromthe foregoing that some of the row and column address combinationsignals are set to logic "high" state initially. Those signals set tologic "high" state initially are determined on the basis of how manypulses of the system clock SC should be generated after the activationof the RAS signal or the CAS signal. As shown in the timing diagram ofFIG. 4C, output data is generated through a data output buffer 400illustrated in FIG. 3 at a rising edge of a pulse P3 of the system clockSC generated after the RAS signal is activated when only the signal RL3among row address combination signals RL2-RLm shown in FIG. 4A issupplied to NAND gate RND3 in logic "high" state. Output data isgenerated through data output buffer 400 illustrated in FIG. 3 at therising edge of the pulse P3 of the system clock SC after the CAS signalis activated when only the signal CL2 among column address combinationsignals CL1-CLn shown in FIG. 4B is supplied to NAND gate CND2 in logic"high" state.

The outputs of NAND gates RND2, and RND4-RNDm (with the exception ofNAND gate RND3) are all in logic "high" state since the potential atnode RN3, an output of the clock stage RCS3, is in logic "high" state.Row address combination signal RL3 is in logic "high" state, and allremaining row address combination signals RL2, RL4-RLm are in logic"low" state.

Meanwhile, data output margin signal PIRD, being generated throughinverters I13 and I14 and connected in series from node RN3 has activecycle in logic "high" state which was delayed three pulses of the systemclock SC compared to the active cycle logic "low" state of the RASsignal. This is because data output margin signal PIRD is extracted fromthird clock stage RCS3 of shift register 110. Accordingly, when dataoutput margin signal PIRD is in logic "high" state active cycle, NANDgate 106 receives the logic "low" state signal supplied from NAND gateRND3 and, as a result, only the RAS latency signal RLINF1 which anoutput from latch circuit RNDL1 is generated in logic "high" state.

As shown in FIG. 3, the RAS latency signal RLINF1 in logic "high" stateis supplied to latency combination circuit 300 and data output marginsignal PIRD is supplied to CAS signal processor 200. In CAS signalprocessor 200 of FIG. 4B, the potential at node CN2 of second clockstage CCS2 goes to logic "high" state at a rising edge of pulse P3 ofthe system clock SC which appears first after the CAS master clock PIChad been activated to logic "high" state. Also, because only the signalCL2 among column address combination signals CL1-CLn is in logic "high"state in accordance with the previously mentioned conditions, only anoutput of NAND gate CND2 among NAND gates CND1-CNDn is generated inlogic "low" state. Moreover, the logic state of data output marginsignal PIRD is reversed and then input into a NOR gate 206 along with awrite master clock signal PIWR which is disabled (logic "low" state)during a read operation. The output of NOR gate 206 is input to NANDgates 208 and 210 of latch circuits CNDL1-CNDLj. Therefore, as in FIG.4A, latch circuits CNDL1-CNDLj generate the CAS latency signalsCLINF1-CLINFj in response to outputs of NAND gates CND1-CNDn.Accordingly, only the CAS latency signal CLINF1 is output to logic"high" state while data output margin signal PIRD is in a logic "high"state active cycle.

The CAS latency signal CLINF1 is supplied along with the RAS latencysignal RLINF1 to latency combination circuit 300 of FIG. 3. Finally, asshown in FIG. 3, only one among RAS latency signals RLINF1-RLINFi inputinto latency combination circuit 300 changes to logic "high" state andonly one among CAS latency signals CLINF1-CLINFj turns to logic "high"state. Accordingly, latency signal RCLAT which is output from latencycombination circuit 300 is generated as logic "high" state before beingsupplied to data output buffer 400. As shown in the timing diagram ofFIG. 4C, data detected from a memory cell through data output buffer 400is output because latency signal RCLAT remains in logic "high" statewhile data output margin signal PIRD is maintained in logic "high"state. It should be particularly noted that 2 bits of the output dataare generated even after the RAS signal enters into the precharge cyclein logic "high" state. By comparison, in conventional memory devices,data cannot be output when the RAS signal is in the precharge cycle.

FIG. 4D illustrates a read timing diagram for the case where data outputmargin signal PIRD is extracted from node RN2 of second clock stageRCS2. This is intended to explain how the number of data bits to beoutput during a RAS precharge cycle can be adjusted freely according toan extracting position of data output margin signal PIRD. The Dataoutput margin signal PIRD is synchronized with the rising edge of thepulse P2 of the system clock SC generated after RAS signal is activatedand then, is activated to logic "high" state.

Also, compared to the CAS activation shown in FIG. 4C, CAS activationshown in FIG. 4C is delayed by one cycle of the system clock SC.Therefore, it becomes apparent that CAS latency signal CLINF1 is inputto latency combination circuit 300 of FIG. 3 after being delayed by onesystem clock cycle when compared to the RAS latency signal RLINF1.Accordingly, the latency signal RCLAT for controlling the data outputbuffer 400 changes to logic "high" state when the RAS and CAS latencysignals RLINF1 and CLINF1 are both enabled to logic "high" state thusenabling data output buffer 400 to output data.

Furthermore, because the activation period of data output margin signalPIRD is shortened by one system clock cycle relative to that of FIG. 4C,the number of output data bits that is secured after the RAS signal isprecharged is equal to one. As shown in FIGS. 4C and 4D, the number ofoutput data bits generated after the RAS signal is precharged accordingto an extracting position of data output margin signal PIRD can beextended or shortened freely before a next RAS cycle begins; that is,during a time span excluding the time required for equalizing andprecharging the input/output lines.

Referring to FIG. 5 showing another embodiment of the present invention,a RAS signal processor 100' and a CAS signal processor 200' respectivelyinclude shift registers each having clock stages similar in structure toshift registers 110 and 210 of FIGS. 4A and 4B. However, the number ofclock stages included in these shift registers each is one less innumber than that of the shift resistors 110 and 210 of FIGS. 4A and 4B.

In addition, a shift stage 350 is connected to an output of latencycombination circuit 300 of FIG. 3 so as to generate the latency signalRCLAT through this shift stage 350. Other configurations are similar instructure and operation as described previously in connection with theembodiment of FIG. 3.

The detailed circuit diagram of RAS signal processor 100' and CAS signalprocessor 200' of FIG. 5 are illustrated respectively in FIGS. 6A and6B.

The timing diagram of FIG. 6C shows a data read operation for the casewhere data output margin signal PIRD is extracted from node RN2 ofsecond stage RCS2 of a shift register of the RAS signal processor 100'shown in FIG. 6A.

The timing diagram of FIG. 6D shows a data read operation for the casewhere data output margin signal PIRD is extracted from node RN1 of firststage RCS1. The operation of the embodiments of the present inventionshown in FIG. 5 and FIGS. 6A-6D correspond substantially with theoperation of the embodiments shown in FIGS. 3-4D and will therefore notbe described further.

In the above discussed embodiments of the present invention, latencysignal RCLAT was described as a signal providing information on the RASsignal and the CAS signal. It can be generated using either the RASsignal or the CAS signal. For example, in case of using the RAS signalonly in the circuit of FIG. 3, one among the RAS latency signalsRLINF1-RLINFi is changed to an active state by using the RAS signalprocessor 100 only, and supplied to the latency combination circuit 300,without configuring the CAS signal processor 200 for generating the CASlatency signal.

As described so far, the memory device of the present invention iscapable of controlling output data in synchronism with the system clockSC supplied from an external source by using the information on the RASand/or the CAS address strobe signals. Therefore, the present inventionallows a memory device that uses a high-frequency clock being suppliedfrom the CPU to effectively control the data output for the fasteroperation speed. Moreover, the present invention is capable ofgenerating normal output data even after the RAS precharge at leastuntil the beginning of the next RAS cycle. Therefore, the presentinvention can generate more output data than the number of output datathat can be generated by the conventional memory devices during one RAScycle.

What is claimed is:
 1. A synchronous semiconductor memory devicecomprising:memory means for storing data; data output buffer means foroutputting data stored in the memory means in response to a data outputbuffer control signal; and latent signal processing means responsive toa clock signal, an address strobe signal and a combination signal forgenerating said data output buffer control signal to control theoutputting of data from said data output buffer, wherein the data outputbuffer control signal generated by said latent signal processing meansis in sync with said clock signal, and is active for at least a firstperiod when said address strobe signal is active as well as for at leasta second period during a memory precharge period when said addressstrobe signal is inactive, said data output buffer outputting datastored in said memory means during both said first and second periods.2. A synchronous semiconductor memory device as defined in claim 1,wherein said address strobe signal is a row address strobe signal.
 3. Asynchronous semiconductor memory device as defined in claim 1, whereinsaid address strobe signal is a column address strobe signal.
 4. Asynchronous semiconductor memory device as defined in claim 1, whereinsaid address strobe signal includes both row and column address strobesignals.
 5. A synchronous semiconductor memory device as defined inclaim 1, wherein said clock signal is supplied from an external source.6. A synchronous semiconductor memory device as defined in claim 1,wherein said combination signal is an address combination signal.
 7. Asynchronous semiconductor memory device including a data output bufferoperating under the control of an address strobe signal and a clocksignal, comprising:shifting means including a plurality of clock stagesfor shifting said address strobe signal therethrough under the controlof said clock signal; means for extracting a data output margin signalfrom a predetermined node of one of said clock stages; and means,responsive to said data output margin signal, input address signals, andoutputs from said clock stages, for generating a data output buffercontrol signal to control the output of data from said data outputbuffer.
 8. A synchronous semiconductor memory device as defined in claim7, wherein said data output buffer control signal is active for at leasta first period when said address strobe signal is active as well as forat least a second period during a memory precharge period when saidaddress strobe signal is inactive, said data output buffer outputtingdata stored in said memory means during both said first and secondperiods.
 9. A synchronous semiconductor memory device as defined inclaim 7, wherein said clock signal is supplied from an external source.10. A synchronous semiconductor memory device including a data outputbuffer operating under the control of a row address strobe signal and acolumn address strobe signal, comprising:first shifting means having aplurality of clock stages for shifting said row address strobe signaltherethrough in response to a clock signal; means for extracting a dataoutput margin signal from a predetermined stage among the clock stagesof said first shifting means; first combining means for generating aplurality of first latency signals in response to row address signals,signals output from said clock stages of said first shifting means, aswell as on the basis of said data output margin signal; second shiftingmeans having a plurality of clock stages for shifting said columnaddress strobe signal therethrough in response to said clock signal;second combining means for generating a plurality of second latencysignals in response to column address signals, signals output from saidclock stages of said second shifting means, as well as on the basis ofsaid data output margin signal; and third combining means responsive tosaid first and second latency signals for generating a data outputbuffer control signal to said data output buffer to control the outputof data from said data output buffer.
 11. A synchronous semiconductormemory device as defined in claim 10, wherein said data output buffercontrol signal is active for at least a first period when said addressstrobe signal is active as well as for at least a second period during amemory precharge period when said address strobe signal is inactive,said data output buffer outputting data stored in said memory meansduring both said first and second periods.
 12. A semiconductor memorydevice as defined in claim 11, wherein said clock signal is suppliedfrom an external source of the semiconductor memory device.